1. Field of Art
Example embodiments relate to a flash memory device and a layout method for the flash memory device, and more particularly, to a nonvolatile memory device which may have an improved bit-line layout and a layout method for the nonvolatile memory device.
2. Description of the Related Art
As mobile systems and other application systems are developed, demands for flash memory may constantly increase. A flash memory device may be a nonvolatile memory device that can be electrically erased and programmed. A non-volatile memory device may be a memory device that can retain stored information even in a state where power is not supplied. In addition, flash memory may consume less power than a storage medium based on magnetic disk memory and may have a fast access time like in a hard disk.
Flash memory may be classified into NOR flash memory and NAND flash memory according to the connection state between cells and bit lines. In particular, NAND flash memory may have a structure in which at least two cell transistors are connected in series to one bit line. In this regard, a large amount of data may be stored in a relatively small area.
In order to improve the characteristic of flash memory, flash memory devices may employ a dummy bit line that is not used to efficiently store data. The dummy bit line may be disposed between main bit lines which may be used to efficiently store data. Wiring disposed above the dummy and main bit lines may be connected to wiring disposed below the dummy and main bit lines via the dummy bit line. As an example, a common source line may be connected to a metal line disposed above the dummy bit line via the dummy bit line.
FIG. 1 is a circuit diagram of a conventional flash memory device 10. Referring to FIG. 1, the conventional flash memory device 10 may include a memory cell array 11 and a page buffer block 12. The memory cell array 11 may include a plurality of memory cells MCs which may be used to store data and a plurality of dummy cells DMCs which may not be used to efficiently store data. In addition, the memory cells MCs may be connected to each of a plurality of main bit lines BLOe through BLOo in series. The dummy cells DMCs may be connected to a dummy bit line DBL in series. In addition, a string selection line SSL, a plurality of word lines WL0 through WL31 and a ground selection line GSL may be disposed parallel to each other.
A common source line CSL may be disposed below the dummy bit line DBL and the main bit lines BL0e through BL0o so as to be approximately perpendicular to the dummy bit line DBL and the main bit lines BL0e through BL0o. A voltage serving as a source voltage of the memory cell MCs may be applied through the common source line CSL. However, a voltage of the common source line CSL may drop due to a resistance component of the common source line CSL, and thus the performance of the flash memory device 10 may deteriorate. In order to reduce or prevent the deterioration of the flash memory device 10, the dummy bit line DBL may be electrically connected to the common source line CSL, and a voltage may be applied to the common source line CSL through the dummy bit line DBL. A reference number “m” of FIG. 1 may refer to a structure whereby the dummy bit line DBL and the common source line CSL may be electrically connected.
FIG. 2 is a circuit diagram of a first page buffer 12_0 which may be included in the page buffer block 12 illustrated in FIG. 1. For example, main bit lines may be classified into even bit lines and odd bit lines. Each of the even bit lines and each of the odd bit lines may be connected to a single page buffer.
A first even bit line BL0e and a first odd bit line BL0o may be connected to the first page buffer 12_0. Generally, a page buffer may include a high voltage region operating at high voltage and a low voltage region operating at low voltage. A plurality of transistors T21 through T24 may be disposed in the high voltage region. The transistors T21 and T22 may be used to precharge and control a voltage of the first even bit line BL0e and a voltage of the first odd bit line BL0o. That is, the transistors T21 and T22 may transfer or shield a bit line power voltage BLPWR in response to shield control signals SHLDe and SHLDo. In addition, the transistors T23 and T24 may be used to select any one of the first even bit line BL0e and the first odd bit line BL0o. That is, the transistors T23 and T24 may connect the even bit line BL0e to a bit line BL0 or may connect the odd bit line BL0o to the bit line BL0, in response to bit line selection signals BLSLTe and BLSLTo.
In the meantime, a transistor T25 disposed in the low voltage region may control the connection between the first even bit line BL0e or the first odd bit line BL0o and the bit line BL0, in response to a shut off control signal BLSHF.
As the integration degree of semiconductor memory devices including flash memory devices increases, the width of and the interval between patterns may be reduced. Double patterning technology (DPT) may reduce the width and the interval of patterns.
When a core part (a memory cell array and a page buffer) of a flash memory device may be embodied based on DPT, the width of and the intervals between patterns used for forming a bit line may be reduced. However, as the intervals between the patterns may become reduced, a larger coupling capacitance may be generated between bit lines adjacent to each other. Likewise, a large coupling capacitance may also be generated between the main bit line BL and the dummy bit line DBL adjacent to the main bit line BL.
In this case, at a point of time of sensing the memory cell MC corresponding to the bit line BL adjacent to the dummy bit line DBL, a voltage of the dummy bit line DBL may drop greatly. Accordingly, since a voltage of the main bit line BL adjacent to the dummy bit line DBL may drop greatly, data of the memory cell MC may not be accurately sensed.
In order to overcome this problem, a bit-line layout and a circuit related to the bit line may be changed. However, the processes involved in performing layout of a bit line using DPT may be complicated and expensive, given that additional operations may be required in order to change the configuration.